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| jpeg2000 video codec data sheet adv202 rev. d information furnished by analog devices is believed to be accurat e and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 C 2012 analog devices, inc. all rights reserved. features complete single - chip jpeg2000 compression and decompression solution for video and still images patented surf? (spatial ultra - efficient recursive filtering) technology enables low power and low cost wavelet - based compression supports both 9/7 and 5/3 wavelet transforms with up to 6 levels of transform programmable tile/image size with widths up to 2048 pixels in 3 - component 4:2:2 interleaved mode, and up to 4096 pixels in single - component mode maximum tile/image width : 4096 pixels video interface directly supporting itu.r - bt656, smpte125m pal/ ntsc, smpte274m, smpte293m (525p), itu.r - bt1358 (625p) or any video format with a maximum input rate of 65 msps for irreversible mode or 40 msps for reversible mode two or more adv202s can be combined to supp ort full - frame smpte274m hdtv (1080i) or smpte296m (720p) flexible asynchronous sram - style host interface allows glueless connection to most 16 - /32 - bit microcontrollers and asics 2.5 v to 3.3 v i/o and 1.5 v core supply 12 mm 12 mm 121 - lead cspbga, speed grade 115 mhz, or 13 mm 13 mm 144 - lead cspbga, speed grade 135 mhz, or 13 mm 13 mm 144 - lead cspbga, speed grade 150 mhz applications networked video and image distribution systems wireless video and image distribution image archival/retrieval digita l cctv and surveillance systems digital cinema systems professional video editing and recording digital still cameras digital camcorders general description the adv202 is a single - chip jpeg2000 codec targeted for video and high bandwidth image compression applications that can benefit from the enhanced quality and feature set provided by the jpeg2000 (j2k) iso/iec15444 - 1 image compression standard. the part implements the computationally intensive operations of the jpeg2000 image compression standard as wel l as providing fully compliant code - stream generation for most applications. the adv202s dedicated video port provides glueless connection to common digital video standards such as itu.r - bt656, smpte125m, smpte293m (525p), itu.r - bt1358 (625p), smpte274m (1080i), or smpte296m (720p). a variety of other high speed, synchronous pixel and video formats can also be sup - ported using the programmable framing and validation signals. (continued on page 4 ) functional block dia gram pixel i/f external dma ctrl pixel fifo code fifo attr fifo wavelet engine internal bus and dma engine embedded risc processor system pixel i/f host i/f ec1 ec2 ram rom ec3 04723-001 adv202 figure 1.
adv202 data sheet rev. d | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 general description ......................................................................... 4 jpeg2000 feature support .......................................................... 4 specifications ..................................................................................... 5 supply voltages and current ...................................................... 5 input/output specifications ........................................................ 5 clock and reset specificati ons ................................................ 6 normal host mode read operation ...................................... 7 normal host mode write operation ..................................... 8 dreq / dack dma mode single fifo write operation .. 9 dreq / dack dma mode single fifo read oper ation . 11 external dma mode fifo write, burst mode .................. 13 external dma mode fifo read, burst mode ................... 14 streaming mode (jdata) fifo read/write ...................... 16 vdata mode timing ............................................................... 17 raw pixel mode timing ............................................................ 18 absolute maximum ratings .......................................................... 19 thermal resistance .................................................................... 19 esd caution ................................................................................ 19 pin bga assignments and function descriptions ................... 20 pin bga assignments ............................................................... 20 pin function descriptions ........................................................ 23 theory of operation ...................................................................... 26 wavelet engine ........................................................................... 26 entropy codecs ........................................................................... 26 embedded processor system .................................................... 26 memory system .......................................................................... 26 internal dma engine ................................................................ 26 adv202 interface ........................................................................... 27 video interface (vdata bus) .................................................. 27 host interface (hdata bus) ................................................... 27 direct and indirect registers .................................................... 27 control access registers ........................................................... 27 pin configuration and bus sizes/modes ................................ 28 stage register .............................................................................. 28 jdata mode ............................................................................... 28 external dma engine ............................................................... 28 internal registers ............................................................................ 29 direct registers ........................................................................... 29 indirect registers ........................................................................ 30 pll ............................................................................................... 31 hardware boot ............................................................................ 31 video input formats ...................................................................... 32 applications ..................................................................................... 34 encode multichip mode ......................................................... 34 decode multichip master/slave ............................................ 35 digital still camera/camcorder .............................................. 35 encode/decode sdtv video application ............................. 36 asic application (32 - bit host/32 - bit asic) ......................... 37 hipi (host interface pixel interface) ................................... 38 jdata interface ......................................................................... 38 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 40 data sheet adv202 rev. d | page 3 of 40 revision history 1/12 rev. c to rev. d updated outline dimensions ........................................................ 39 changes to ordering guide ........................................................... 40 11 /06 rev. b to rev. c deleted anc fifo references ........................................ universal changes to features .......................................................................... 1 chan ges to figure 1 ........................................................................... 1 changes to jpeg2000 feature support section ............................ 4 cha nges to figure 8 ......................................................................... 10 changes to figure 10 ...................................................................... 11 changes to figure 12 ...................................................................... 12 changes to external dma mode fifo write, burst mode section ......................................................................... 13 changes to external dma mode fifo read, burst mode section ......................................................................... 13 changes to table 11 ........................................................................ 1 7 changes to figure 22 ...................................................................... 1 8 deleted spi po rt timing section .................................................. 18 added absolute maximum ratings section ............................... 19 change s to pin bga assignments and function descriptions section ....................................................................... 20 changes to adv202 i nterface section ........................................ 27 changes to table 19 ........................................................................ 29 changes to indirect registers section .......................................... 30 changes to pll sectio n .................................................................. 31 changes to table 23 ........................................................................ 31 changes to video input formats section .................................... 32 changes to figure 24 ...................................................................... 34 changes to figure 26 ...................................................................... 35 changes to ordering guide ........................................................... 40 1/05 rev. a to rev. b updated outline dimensions ........................................................ 39 12/04 rev. 0 to rev. a changes to features .......................................................................... 1 changes to t able 2 ............................................................................ 4 changes to table 16 ........................................................................ 24 changes to table 23 ........................................................................ 32 7/04 revision 0: initial version adv202 data sheet rev. d | page 4 of 40 general description (continued from page 1) the adv202 can process images at a rate of 40 msps in reversible mode and at higher rates when used in irreversible mode . the adv202 contains a dedicated wavelet transform engine, three entropy codecs, an on - board memory system, and an embedded risc processor that can provide a complete jpeg2000 compression/decompression solution. the wavelet processor supports the 9/7 irre versible wavelet transform and the 5/3 wavelet transform in reversible and irreversible modes. the entropy codecs support all features in the jpeg2000 part 1 specification, except maxshift roi. the adv202 operates on a rectangular array of pixel samples ca lled a tile. a tile can contain a complete image, up to the maximum supported size, or some portion of an image. the maximum horizontal tile size supported depends on the wavelet transform selected and the number of samples in the tile. images larger than the adv202s maximum tile size can be broken into individual tiles and then sent sequentially to the chip while still maintaining a single, fully compliant jpeg2000 code stream for the entire image. jpeg2000 feature sup port the adv202 supports a broad set of features that are included in part 1 of the jpeg2000 standard (iso/iec 15444). see getting started with adv202 for information on the jpeg2000 features that the adv202 currently supports. depending on the particular application requirements, the adv202 can provide varying levels of jpeg2000 compression support. it can provide raw code - block and att ribute data output, which allow the host software to have complete control over the generation of the jpeg2 000 code stream and other aspects of the compression process such as bit - rate control. otherwise, the adv202 can create a complete, fully compliant jpeg2000 code stream (.j2c) and enhanced file formats such as .jp2 and .j2c. see getting started with adv202 for information on the formats that the adv202 currently supports. application notes and other adv202 support documents can be accessed over the adv202 product page at: ? http://www.analog.com/adv202notes or from ? ftp://ftp.analog.com/pub/digital_imaging/adv202_ftp_s ite_contents_3.html data sheet adv202 rev. d | page 5 of 40 specifications supply voltages and cur rent table 1 . parameter description min typ max unit vdd dc supply voltage, core 1.425 1.5 1.575 v iovdd dc supply voltage, i/o 2.375 3.3 3.63 v pllvdd dc supply voltage, pll 1.425 1.5 1.575 v v input in put range ?0.3 v ddi/o + 0.3 v temp operating ambient temperature range in free air ?40 +25 +85 c i dd static current 1 300 ma dynamic current, core (jclk frequency = 150 mhz) 2 570 ma dynamic current, core (jclk frequency = 108 mhz) 420 ma dy namic current, core (jclk frequency = 81 mhz) 325 ma dynamic current, i/o 20 ma dynamic current, pll 2.6 ma 1 no clock or i/o activity. 2 adv202 - 150 only. input/output specifi cations table 2 . parameter description test conditions min typ max unit v ih (3.3 v) high level input voltage vdd = max 2.2 v v ih (2.5 v) high level input voltage vdd = max 1.9 v v il (3.3 v, 2.5 v) low level input voltage vdd = min 0.6 v v oh (3.3 v) high level output voltage vdd = min, i oh = ?0.5 ma 2.4 v v oh (2.5 v) high level output voltage vdd = min, i oh = ?0.5 ma 2.0 v v ol (3.3 v, 2.5 v) low level output voltage vdd = min, i ol = 2 ma 0.4 v i ih high level input current vdd = max, v in = vdd 1.0 a i il low level input current vdd = max, v in = 0 v 1 a i ozh high level three - state leakage current vdd = max, v in = vdd 1.0 a i ozl low level three - state leakage current vdd = max, v in = 0 v 1.0 a c i input pin capacitance 8 pf c o output pin capacitan ce 8 pf adv202 data sheet rev. d | page 6 of 40 clock and reset specifications table 3 . parameter description min typ max unit t mclk mclk 1 period 13.3 100 ns t mclkl mclk width low 6 ns t mclkh mclk width high 6 ns t vclk vclk period 13.4 50 ns t vclkl vclk width low 5 ns t vclkh vclk width high 5 ns t rst reset width low 5 mclk cycles 1 for a definition of mclk, see the pll section. 04723-010 mclk vclk t mclk t mclkh t mclk l t vclk t vclkh t vclk l figure 2 . input clock data sheet adv202 rev. d | page 7 of 40 normal host mode read operation table 4 . parameter description min typ max unit t ack [dir] rd to ack , direct registers and fifo accesses 5 1.5 jclk 1 + 7.0 ns t ack [indir] rd to ack , indirect registers 10.5 jclk 15.5 jclk + 7.0 ns t drd [dir] read access time, direct registers 5 1.5 jclk + 7.0 ns t drd [indir] read access time, indirect registers 10.5 jclk 15.5 jclk + 7.0 ns t hzr d data hold 2 8.5 ns t sc cs to rd setup 0 ns t sa address setup 2 ns t hc cs hold 0 ns t ha address hold 2 ns t rh read inactive pulse width 2.5 jclk t rl read active pulse width 2.5 jclk t rcyc read cycle time, direct registers 5.0 jclk 1 for a definition of jclk, see the pll section. 04723-0 1 1 addr hd at a t sa t sc t hc t rl t ack t drd t hzrd t rh t rcyc t ha cs rd ack v alid figure 3 . normal host mode read operation adv202 data sheet rev. d | page 8 of 40 normal host mode write operation table 5 . parameter description min typ max unit t ack (direct) we to ack , direct registers and fifo accesses 5 1.5 jclk 1 + 7.0 ns t ack (indirect) we to ack , indirect registers 5 2.5 jclk + 7.0 ns t sd data setup 3.0 ns t hd data hold 1.5 ns t sa address setup 2 ns t ha address hold 2 ns t sc cs to we setup 0 ns t hc cs hold 0 ns t wh write inactive pulse width (minimum time until next we pulse) 2.5 jclk t wl write active pulse width 2.5 jclk t wcyc write cycle time 5 jclk 1 for a definition of jclk, see the pll section. 04723-012 addr hd at a t sa t sc t hc t wl t ack t hd t sd t wh t wcyc t ha cs we ack v alid figure 4 . no r / mal host mode write operation data sheet adv202 rev. d | page 9 of 40 dreq / dack dma mode single fifo write op eration table 6 . parameter description min typ max unit dreq pulse 1 dreq pulse width 1 15 jclk cycles 2 t dreq dack assert to subsequent dreq delay 2.5 3.5 jclk + 7.5 ns jclk cycles t we su we to dack setup 0 ns t su data to dack deassert setup 2 ns t hd data to dack deassert hold 2 ns dack lo dack assert pulse width 2 jclk cycl es dack hi dack deassert pulse width 2 jclk cycles t we hd we hold after dack deassert 0 ns w fsrq we assert to fsrq deassert (fifo full) 1.5 2.5 jclk + 7.5 ns jclk cycles t dreq rtn dack to dreq deassert (dr puls = 0) 2.5 3.5 jclk + 7.5 ns jclk cycl es 1 applies to assigned dma channel, if edmod0 or edmod1[14:11] is programmed to a value that is not 0. pulse width depends on the value programmed 2 for a definition of jclk, see the pll section. 04723-013 we dack dreq hd at a 3 2 1 0 dreq pulse t dreq dack hi dack lo t wesu t su t hd t wehd figure 5 . single write for dreq / dack dma mode for assigned dma channel (edmod0/edmod1 [ 14:11] not programmed to a value of 0000) 04723-014 we dack dreq hd at a 0 1 2 t dreqrtn dack hi dack lo t wesu t su t hd t wehd figure 6 . single writ e for dreq / dack dma mode for assigned dma channel (edmod0/edmod1 [ 14:11] programmed to a value of 0000) adv202 data sheet rev. d | page 10 of 40 04723-015 wefb dack dreq hd at a 0 1 2 dreq pulse t dreq dack hi dack lo t wesu t su t hd t wehd figure 7 . fly - by dma mode single write cycle ( dreq puls e width is programmable) 04723-016 fsrq0 we fsc0 hd at a wfsrq fifo not ful l fifo ful l not written t o fifo 0 1 2 t su t hd figure 8 . dcs dma mode single write access (rev. 0.1 and higher) data sheet adv202 rev. d | page 11 of 40 dreq / dack dma mode single fifo read ope ration table 7 . parameter d escription min typ max unit dreq pulse dreq pulse width 1 1 15 jclk cycles 2 t dreq dack assert to subsequent dreq delay 2.5 3.5 jclk + 7.5 ns jclk cycles t rd su rd to dack setup 0 ns t rd dack to data valid 2.5 11 ns t hd data hold 1.5 ns dack lo dack assert pulse width 2 jclk cycles dack hi dack deassert pulse width 2 jclk cycles t rd hd rd hold after dack de assert 0 ns rd fsrq rd assert to fsrq deassert (fifo empty) 1.5 2.5 jclk + 7.5 ns jclk cycles t dreq rtn dack to dreq deassert (dr puls = 0) 2.5 3.5 jclk + 7.5 ns jclk cycles 1 applies to assigned dma channel, if edmod0 or edmod1[14:11] is programmed to a nonzero value. 2 for a definition of j c lk , see the pll section. 04723-018 rd dack dreq hd at a 0 1 2 t rd t hd dreq pulse t dreq t rdsu t rdhd dack hi dack lo figure 9 . single read for dreq / dack dma mode for assigned dma channel (edmod0/edmod1 [ 14:11 ] not programmed to a value of 0000) 04723-019 rd dack dreq hd at a 0 1 2 t rd t hd t dreqrtn t rdsu t rdhd dack hi dack lo figure 10 . single read for dreq / dack dma mode for assigned dma channel (edmod0/edmod1 [ 14:11] programmed to a value of 0000) adv202 data sheet rev. d | page 12 of 40 04723-020 rdfb dack dreq hd at a 0 1 2 t rd t hd t dreq dreq pulse t rdsu t rdhd dack hi dack lo figure 11 . fly - by dma mode single read cycle ( dreq pulse width is programmable) 04723-021 rd fsrq0 fcs0 hd at a 0 1 rdfsrq fifo not empt y fifo empt y t rd t hd figure 12 . dcs dma mode single read access (rev. 0.1 and higher) data sheet adv202 rev. d | page 13 of 40 external dma mode fifo write, burst mo de table 8 . parameter description min typ max unit dreq pulse dreq pulse width 1 1 15 jclk 2 cycles t dreq rtn we to dreq deass ert (dr pulse = 0) 2.5 3.5 jclk + 7.5 ns jclk cycles t dack su dack to we setup 0 ns t su data setup 2.5 ns t hd data hold 2 ns we lo we assert pulse width 1.5 jclk cycles we hi we deassert pulse width 1.5 jclk cycles t dreq wait last burst access to next dreq 2.5 4.5 jclk + 7.5 ns 3 jclk cycles 1 applies to assigned dma channel , i f edmod0 or edmod1[14:11] is pr ogrammed to a value that is not 0. pulse width depends on the value programmed. 2 for a definition of j clk , see the pll section. 3 if sufficient space is available in fifo. 04723-022 dreq dack we hd at a we hi we lo t dacksu t hd t su 0 1 13 14 15 t dreq w ait dreq pulse figure 13 . burst write cycle for dreq /dma mode for assigned dma channel (edmod0/edmod1 [ 14:11] not programmed to a value of 0000) 04723-023 dreq dack we hda t a we hi we lo t dacksu t hd t su 0 1 13 14 15 t dreqw ait t dreqrtn figure 14 . burst write cycle for dreq /dma mode for assign ed dma channel (edmod0/edmod1 [ 14:11] programmed to a value of 0000) adv202 data sheet rev. d | page 14 of 40 04723-024 dreq dack wefb hd at a we hi we lo t dacksu t hd t su 0 1 13 14 15 t dreq w ait t dreqrtn figure 15 . burst write cycle for fly - by dma mode ( dreq pulse width is programmable) ex ternal dma mode fifo read, burst mod e table 9 . parameter description min typ max unit dreq pulse dreq pulse width 1 1 15 jclk cycles 2 t dreq rtn rd to dreq deassert (dr puls = 0) 2.5 3.5 jclk + 7.5 ns jclk cycles t dack su dack to rd setup 0 ns t rd rd to data valid 2.5 9.7 ns t hd data hold 2.5 ns rd lo rd assert pulse width 1.5 jclk cycles rd hi rd deassert pulse width 1.5 jclk cycles t dreq wait last burst access to next dreq 2.5 3.5 jclk + 7.5 ns 3 jclk cycles 1 applies to assigned dma channel , if edmod0 or edmod1 [14:11] is programmed to a value that is not 0. pulse width depends on the value programmed. 2 for a definition of j clk , see the pll section. 3 if sufficient space is available in fifo. 04723-025 dreq dack rd hd at a rd hi rd lo t dacksu t hd 0 1 13 14 15 t dreq w ait dreq pulse t rd figure 16 . burst read cycle for dreq / dack dma mode for assi gned d ma channel (emod0/edmod1 [ 14:11] not programmed to a value of 0 ) data sheet adv202 rev. d | page 15 of 40 04723-026 dreq dack rd hd a t a rd hi rd lo t dacksu t hd 0 1 13 14 15 t dreq w ait t dreqrtn t rd figure 17 . burst read cycle for dreq / dack dma mode for assig ned dma channel ( emod0/edmod1 [ 14:11] programmed to a val ue of 0000) 04723-027 dreq dack rdfb hd a t a t dacksu t hd 0 1 13 14 15 t dreqwait t dreqrtn t rd figure 18 . bu rst read cycle, fly - by dma mode ( dreq pulse width is programmable) adv202 data sheet rev. d | page 16 of 40 streaming mode (jdat a) fifo read/write table 10. parameter description min typ max unit jdata td mclk to jdata valid 1.5 2.5 jclk + 7.0 ns jclk cycles 1 valid td mclk to valid assert/deassert 1.5 2.5 jclk + .7.0 ns jclk cycles hold su hold setup to rising mclk 3 ns hold hd hold hold from rising mclk 3 ns jdata su jdata setup to rising mclk 3 ns jdata hd jdata hold from rising mclk 3 ns 1 for a definition of j clk , see the pll section. 04723-028 mclk jd at a v alid hold hold hd hold su v alid td jd at a su jd at a td jd at a hd figure 19 . streaming mode timing encode mode jdata output 04723-029 mclk jd at a v alid hold hold hd hold su v alid td jd at a su jd at a hd figure 20 . streaming mode timing decode mode jdata in put data sheet adv202 rev. d | page 17 of 40 vdata mode timing table 11. parameter description min typ max unit vdata td vclk to vdata valid delay (vdata output) 12 ns vdata su vdata setup to rising vclk (vdata input) 4 ns vdata hd vdata hold from rising vc lk (vdata input) 4 ns hsync su hsync setup to rising vclk 3 ns hsync hd hsync hold from rising vclk 4 ns hsync td vclk to hsync valid delay 12 ns vsync su vsync setup to rising vclk 3 ns vsync hd vsync hold from rising vclk 4 ns vsync td vclk to vsync valid delay 12 ns field su field setup to rising vclk 4 ns field hd field hold from rising vclk 3 ns field td vclk to field valid 12 ns sync delay decode data sync delay for hd input with eav/sav codes 7 vclk cycles decode data sync delay for sd input with eav/sav codes 9 vclk cycles decode data sync delay for hvf input (from first rising vclk after hsync low to first data sample) 10 vclk cycles 04723-030 cr y cb y ff ea v ff sa v cb y cr vdat a hd vdat a su vclk vdat a(in) encode ccir-656 line vdat a td vclk vdat a(out) vdat a(out) cr y cb y ff ea v ff sa v cb y cr decode master ccir-656 line vclk vdat a(out) vdat a td sync del a y cr y y cb y ff ea v ff sa v cb y *hsync and vsync do not h a ve t o be applied simu lt aneous l y vclk vdat a(in) hsync vsync cr y y cb y cr y cb y y cr y cb cb hsync su encode hvf mode decode sl a ve ccir-656 line hsync hd vsync su vsync hd cb y cr y cb cb y vclk hsync vsync decode sl a ve hvf mode hsync hd * vdat a td sync del a y vsync hd * cb y cr y figure 21 . video mode timing adv202 data sheet rev. d | page 18 of 40 raw pixel mode timing table 12. parameter description min typ max unit vdata td vclk to pixeldata valid delay (pixeldata output) 12 ns vdata su pixeldata setup to rising vclk (pixeldata input) 4 ns vdata hd pixeldata hold from risin g vclk (pixeldata input) 4 ns vrdy td vclk to vrdy valid delay 12 ns vfrm su vfrm setup to rising vclk (vframe input) 3 ns vfrm hd vfrm hold from rising vclk (vframe input) 4 ns vfrm td vclk to vfrm valid delay (vframe output) 12 ns vstrb su vstrb setup to rising vclk 4 ns vstrb hd vstrb hold from rising vclk 3 ns n n 0 1 2 04723-031 vclk vclk pixe l da t a(in) pixe l da t a vfrm(out) vfrm(in) vrd y vstrb n?1 n 0 1 2 vrfm td vda t a td vstrb su vstrb hd vfrm su vfrm hd vd a t a hd vda t a su vrd y td ra w pixe l mode ? encode ra w pixe l mode ? decode figure 22 . raw pixel mode timing data sheet adv202 rev. d | page 19 of 40 absolute maximum rat ings table 13. parameter rating vdd ( supply voltage, c ore ) ? 0.3 v to +1.65 v iovdd ( supply voltage, i/o) ? 0.3 v to + iovdd + 0.3 v pllvdd ( supply v oltage, pll ) ? 0.3 v to +1.65 v storage temperature ( t s ) range ? 65 c to 150 c stresses above those listed under absolute maximum ratings may cause permanent damage t o the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 14 . thermal resistance package type ja jc unit adv202 (144 - lead ) 22.5 3.8 c/w adv202 (121 - lead ) 32 .8 7.92 c/w esd caution adv202 data sheet rev. d | page 20 of 40 pin bga assignments and function descrip tions pin bga assignments table 15 . pin bga assignments for 121 - lead package pin. no. pin location pin description 1 a1 dgnd 2 a2 hdata[2] 3 a3 vdd 4 a4 dgnd 5 a5 hdata[0] 6 a6 hdata[1] 7 a7 vdata[1] 8 a8 vdd 9 a9 dgnd 10 a10 vdata[0] 11 a11 dgnd 12 b1 hdata[3] 13 b2 hdata[4] 14 b3 hdata[5] 15 b4 hdata[7] 16 b5 hdata[8] 17 b6 iovdd 18 b7 vdata[6] 19 b8 vdata[5] 20 b9 vdata[4] 21 b10 vdata[2] 22 b11 vdata[3] 23 c1 dgnd 24 c2 hdata[6] 25 c3 hdata[9] 26 c4 hdata[10] 27 c5 hdata[11] 28 c6 iovdd 29 c7 vdata[9] 30 c8 iovdd 31 c9 vdata[8] 32 c10 vdata[7] 33 c11 dgnd 34 d1 hdata[12] 35 d2 hdata[13] 36 d3 hdata[14] 37 d4 hdata[15] 38 d5 iovdd 39 d6 dgnd 40 d7 vdd 41 d8 vsync 42 d9 hsync 43 d10 vdata[10] 44 d11 vdata[11] 45 e1 dgnd 46 e2 hdata[18]_vdata[14] 47 e3 hdata[17 ]_vdata[13] 48 e4 hdata[16 ]_vdata[12] 49 e5 dgnd pin. no. pin location pin description 50 e6 dgnd 51 e7 dgnd 52 e8 iovdd 53 e9 vclk 54 e10 field 55 e11 dgnd 56 f1 dgnd 57 f2 hdata[19 ]_vdata[15] 58 f3 hdata[20] 59 f 4 hdata[21] 60 f5 dgnd 61 f6 dgnd 62 f7 dgnd 63 f8 dreq0 64 f9 dack0 65 f10 dreq1 66 f11 dgnd 67 g1 dgnd 68 g2 hdata[22] 69 g3 hdata[23] 70 g4 hdata [24]_jdata[0] 71 g5 dgnd 72 g6 dgnd 73 g7 dgnd 74 g8 iovdd 75 g9 dack1 76 g10 irq 77 g11 dgnd 78 h1 hdata[28]_jdata[4] 79 h2 hdata[27 ]_jdata[3] 80 h3 hdata[26 ]_jdata[2] 8 1 h4 hdata[25 ] _jdata[1] 82 h5 iovdd 83 h6 dgnd 84 h7 vdd 85 h8 ack 86 h9 rd 87 h10 addr[1] 88 h11 addr[3] 89 j1 dgnd 90 j2 hdata[31]_jdata[7] 91 j3 hdata[30]_jdata[6] 9 2 j4 hdata[29]_jdata[5] 93 j5 iovdd 94 j6 test1 95 j7 we 96 j8 cs 97 j9 addr[0] data sheet adv202 rev. d | page 21 of 40 pin. no. pin location pin description 98 j10 test3 99 j11 dgnd 100 k1 scomm[4] 101 k2 scomm[3] 102 k3 scomm[0] 103 k4 scomm[1 ] 104 k5 iovdd 105 k6 iovdd 106 k7 iovdd 107 k8 addr[2] 108 k9 test2 109 k10 test5 pin. no. pin location pin description 110 k11 dgnd 111 l1 dgnd 112 l2 scomm[7] 113 l3 scomm[6] 114 l4 scomm[5] 115 l5 scomm[2] 116 l6 test4 117 l7 reset 118 l8 dgnd 119 l9 mclk 120 l10 pllvdd 121 l11 dgnd table 16 . pin bga assignments for 144 - lead package pin no. pin location pin description 1 a1 dgnd 2 a2 hdata[2] 3 a3 hdata[1] 4 a4 hdata[0] 5 a5 dgnd 6 a6 dgnd 7 a7 dgnd 8 a8 dgnd 9 a9 vdata[2] 10 a10 vdata[1] 11 a11 vdata[0] 12 a12 dgnd 13 b1 hdata[5] 14 b2 hdata[4] 15 b3 hdata[3] 16 b4 iovdd 17 b5 dgnd 18 b6 vdd 19 b 7 vdd 20 b8 dgnd 21 b9 iovdd 22 b10 vdata[5] 23 b11 vdata[4] 24 b12 vdata[3] 25 c1 hdata[8] 26 c2 hdata[7] 27 c3 hdata[6] 28 c4 iovdd 29 c5 dgnd 30 c6 vdd 31 c7 vdd 32 c8 dgnd 33 c9 iovdd 34 c10 vdata[8] 35 c11 vdata[7] 36 c12 vdata[6] 37 d1 hdata[11] pin no. pin location pin description 38 d2 hdata[10] 39 d3 hdata[9] 40 d4 iovdd 41 d5 dgnd 42 d6 vdd 43 d7 vdd 44 d8 dgnd 45 d9 iovdd 46 d10 vdata[11] 47 d11 vdata[10] 48 d12 vdata[9 ] 49 e1 hdata[14] 50 e2 hdata[13] 51 e3 hdata[12] 52 e4 dgnd 53 e5 dgnd 54 e6 dgnd 55 e7 dgnd 56 e8 dgnd 57 e9 field 58 e10 vsync 59 e11 hsync 60 e12 vclk 61 f1 hdata[18]_vdata[14] 62 f2 hdata[17 ]_vdat a[13] 63 f3 hdata[16 ]_vdata[12] 64 f4 hdata[15] 65 f5 dgnd 66 f6 dgnd 67 f7 dgnd 68 f8 dgnd 69 f9 dack1 70 f10 dreq1 71 f11 dack0 72 f12 dreq0 73 g1 hdata[22] 74 g2 hdata[21] adv202 data sheet rev. d | page 22 of 40 pin no. pin location pin description 75 g3 hdata[20] 76 g4 hdata[19 ]_vdata[15] 77 g5 dgnd 78 g6 dgnd 79 g7 dgnd 80 g8 dgnd 81 g9 dgnd 82 g10 irq 83 g11 ack 84 g12 rd 85 h1 hdata[26]_jdata[2] 86 h2 hdata[25]_jdata[1] 87 h3 hdata[24]_jdata[0] 88 h4 hdata[23] 89 h5 dgnd 90 h6 dgnd 91 h7 dgnd 92 h8 dgnd 93 h9 dgnd 94 h10 wr 95 h 11 cs 96 h12 addr[0] 97 j1 hdata[30]_jdata[6] 98 j2 hdata[29]_jdata[5] 99 j3 hdata[28]_jdata[4] 100 j4 hdata[27]_jdata[3] 101 j5 dgnd 102 j6 vdd 103 j7 vdd 104 j8 dgnd 105 j9 dgnd 106 j10 addr[1] 107 j11 addr[2] 108 j12 addr[3] 109 k1 scomm[1] pin no. pin location pin description 110 k2 scomm[0] 111 k3 hdata[31]_jdata[7] 112 k4 iovdd 113 k5 dgnd 114 k6 vdd 115 k7 vdd 116 k8 dgnd 117 k9 iovdd 118 k10 test3 119 k11 test2 120 k12 test1 121 l1 scomm[4] 122 l2 scomm[3] 123 l3 scomm[2] 124 l4 iovdd 125 l5 dgnd 126 l6 vdd 127 l7 vdd 128 l8 dgnd 129 l9 iovdd 130 l10 test5 131 l11 reset 132 l12 mclk 133 m1 dgn d 134 m2 scomm[7] 135 m3 scomm[6] 136 m4 scomm[5] 137 m5 dgnd 138 m6 dgnd 139 m7 dgnd 140 m8 dgnd 141 m9 test4 142 m10 pllvdd 143 m11 dgnd 144 m12 dgnd data sheet adv202 rev. d | page 23 of 40 pin function descrip tions table 17. mnemonic pins used 121- lead package 144- lead package i/o description mclk 1 l9 l12 i system input clock. for details, see the pll section. maximum input frequency on mclk is 74.25 mhz. reset 1 l7 l 11 i reset. causes the adv202 to immediately reset. cs , rd , we , dack0 , dack1 , dreq0 , and dreq1 must be held high when a reset is applied. hdata[15:0] 16 d4 to d1, c5 to c3, b5, b4, c2, b3 to b1, a2, a6 to a5 f4, e1 to e3, d1 to d3, c1 to c3, b1 to b3, a2, a3, a4 i/o host data bus. with hdata[23:16], [27:24], [31:28], these pins make up the 32 - bit wide host data bus. the async host interface is interfaced together with addr[3:0], cs , we , rd , and ack . unused hdata pins should be pulled down via a 10 k? resistor. addr[3:0] 4 h11, k8, h10, j9 j12, j11, j10, h12 i address bus for the host interface. cs 1 j8 h11 i chip select. this signal is used to qualify addressed read and write access to the adv202 using the hos t interface. we 1 j7 h10 i write enable used with the host interface. rdfb read enable when fly - by dma is enabled. note: simultaneous assertion of we and dack low activates the hdata bus, even if the dma channels are disabled. rd 1 h9 g12 i read enable. used with the host interface. wefb write enable when fly - by dma is enabled. note: simultaneous assertion o f rd and dack low activates the hdata bus, even if the dma channels are disabled. ack 1 h8 g11 o acknowledge. used for direct register accesses. this signal indicates that the last re gister access was successful. note: due to synchronization issues, control and status register accesses can incur an additional delay, so the host software should wait for acknowledgment from the adv202 . accesses to the fifos (external dma modes), on the other hand, are guaranteed to occur immediately, if space is available, and should not wait for ack , if the t iming constraints are observed. if ack is shared with more than one device, ack should be connected to a pull - up resistor (10 k?) and the pll_hi register, bit 4, must be set to 1. irq 1 g10 g10 o interrupt. this pin indicates that the adv202 requires the attention of the host processor. this pin can be programmed to indicate the status of the inter nal interrupt conditions within the adv202. the interrupt s ources are enabled via bits in r egister eirqie. dreq0 1 f8 f12 o data request for external dma interface. indicates that the adv202 is ready to send/receive data to/from t he fifo assigned to dma channel 0. fsrq0 o used in dcs - dma mode. service request from the fifo assigned to channel 0 (asynchronous mode). valid o valid indication for jdata input/output stream. po larity of this pin is programmable in the edmod0 register. valid is always an output. cfg[1] i boot mode configuration. this pin is read on reset to determine the boot configuration of the on - board processor. the pin should be tied to iovdd or dgnd through a 10 k ? resistor. dack0 1 f9 f11 i data acknowledge for external dma interface. signal from the host cpu, which indicates that the data transfer request ( dreq0 ) has been acknowledged and data transfer can proceed . this pin must be held high at all times if the dma interface is not used, even if the dma channels are disabled. adv202 data sheet rev. d | page 24 of 40 mnemonic pins used 121- lead package 144- lead package i/o description hold i external hold indication for jdata input/output stream. polarity is programmable in the edmod0 register. th is pin is always an input. fcs0 i used in dcs - dma mode. chip select for the fifo assigned to channel 0 (asynchronous mode). dreq1 1 f10 f10 o data request for external dma interface. indicates that the adv202 is ready to send/receive data to/from the fifo assigned to dma channel 1. fsrq1 o used in dcs - dma mode. service request from the fifo assigned to channel 1 (asynchronous mode). cfg[2] i boot mode configurati on. this pin is read on reset to determine the boot configuration of the on - board processor. the pin should be tied to iovdd or dgnd through a 10 k ? resistor. dack1 1 g9 f9 i data acknowledge for external dma interface. signal from the host cpu, which indicates that the data transfer request ( dreq1 ) has been acknowledged and data transfer can proce ed. this pin must be held high at all times unless a dma or jdata access is occurring. this pin must be held high at all times if the dma interface is not used, even if the dma channels are disabled. fcs1 i used in dcs - dma mode . chip select for the fifo assigned to channel 1 (asynchronous mode). hdata[31:28] 4 j2 to j4, h1 k3, j1 to j3 i/o host expansion bus. jdata[7:4] i/o jdata bus (jdata mode). hdata[27:24] 4 h2 to h4, g4 j4, h1 to h3 i/o host expansion bu s. jdata[3:0] i/o jdata bus (jdata mode). hdata[23:16] 8 g3, g2, f4, f3, f2 e2, e3, e4 h4, g1 to g4, f1 to f3 i/o host expansion bus. scomm[7] 8 l2 m2 i/o w hen not used, this pin should be tied low via a 10 k ? r esistor. scomm[6] l3 m3 i/o w hen not used, this pin should be tied low via a 10 k? r esistor. scomm[5] l4 m4 i/o t his pin must be used in multiple chip mode to align the outputs of two or more adv202s. for details, see the applications section and an -796 adv202 multichip application application note. when not used, this pin should be tied low via a 10 k? resistor. scomm[4] k1 l1 o lcode output in encode mode. when lcode is enabled, the ou tput on this pin indicates on a high transition that the last data - word for a field has been read from the fifo. for an 8 - bit interface, such as jdata, lcode is asserted for four consecutive bytes and is enabled by default. scomm[3] k2 l2 o this pin s h ould be tied l ow via a 10 k ? r esistor. scomm[2] l5 l3 o t his pin should be tied low via a 10 k? r esistor. scomm[1] k4 k1 i t his pin should be tied low via a 10 k? r esistor. scomm[0] k3 k2 o t his pin should be tied low via a 10 k? r esistor. vclk 1 e9 e12 i vi deo data clock. must be supplied if video data is input/output on the vdata bus. vdata[11:0] 12 d11, d10, c7, c9, c10, b7, b8, b9, b11, b10, a7, a10 d10 to d12, c10 to c12, b10 to b12, a9 to a11 i/o video data. unused pins should be pulled down vi a a 10 k? resistor. vsync 1 d8 e10 i/o vertical sync for video mode. vfrm raw pixel mode framing signal. indicates first sample of a tile when asserted high. hsync 1 d9 e11 i/o horizontal sync for video mode. vrdy o raw pixel mode ready signal. data sheet adv202 rev. d | page 25 of 40 mnemonic pins used 121- lead package 144- lead package i/o description field 1 e10 e9 i/o field sync for video mode. vstrb i raw pixel mode transfer strobe. test1 1 j6 k12 i t his pin should be connected to ground via a pull - down resistor. test2 1 k9 k11 i t his pin should be connected to ground via a pull - down resistor. test3 1 j10 k10 i t his pin should be connected to ground via a pull - down resistor. test4 1 l6 m9 i t his pin should be connected to ground via a pull - down resistor. test5 1 k10 l10 o no connect. vdd a3, a8, d7 , h7 b6, b7, c6, c7, d6, d7, j6, j7, k6, k7, l6, l7 v positive supply for core. dgnd a1, a11, a4, a9, c1, c11, d6, e1, e5 to e7, e11, f1, f5 to f7, f11, g1, g5 to g7, g11, h6, j1, j11, k11, l1, l8, l11 a1, a5 to a8, a12, b5, b8, c5, c8, d5, d8, e4 t o e8, f5 to f8, g5 to g9, h5 to h9, j5, j8 to j9, k5, k8, l5, l8, m1, m5 to m8, m11, m12 gnd ground. pllvdd 1 l10 m10 v positive supply for pll. iovdd b6, c6, c8, d5, e8, g8, h5, j5, k5, k6, k7 b4, b9, c4, c9, d4, d9, k4, k9, l4, l9 v positi ve supply for i/o. adv202 data sheet rev. d | page 26 of 40 theory of operation the input video or pixel data is passed on to the adv202s pixel interface, where samples are de - interleaved and passed on to the wavelet engine, which decomposes each tile or frame into subbands using the 5/3 or 9/7 filters. the resulting wavelet coefficients are then written to internal memory. next, the entropy codecs code the image data so it conforms to the jpeg2000 standard. an internal dma provides high bandwidth memory - to - memory transfers, as well as high performance transfers between functional blocks and memory. wavelet engine the adv202 provides a dedicated wavelet t ransform processor based on analog devices proven and patented surf technology. this processor can perform up to six wavelet decomposition levels on a tile. in encode mode, the wavelet transform processor takes in uncompressed samples, performs the wavelet transform and quantization, and writes the wavelet coefficients in all frequency subbands to internal memory. each of these subbands is t hen further broken down into code blocks. the code - block dimensions can be user - defined and are used by the wavelet transform processor to organize the wavelet coefficients into code blocks when writing to internal memory. each completed code block is then entropy coded by one of the entropy codecs. in decode mode, wavelet coefficients are read from internal memory and recomposed into uncompressed samples. entropy codecs the entropy codec block performs context modeling and arithmetic coding on a code blo ck of the wavelet coefficients. additionally, this block performs the distortion metric calculations during compression that are required for optimal rate and distortion performance. because the entropy coding process is the most computationally intensive operation in the jpeg2000 compression process, three dedicated hardware entropy codecs are provided on the adv202. embedded processor s ystem the adv202 incorporates an embedded 32 - bit risc processor. this processor is used for configuration, control, and m anage - ment of the dedicated hardware functions, as well as for parsing and generating the jpeg2000 code stream. the processor system includes memory for both program and data memory, an interrupt controller, standard bus interfaces, and other hardware func tions such as timers and counters. memory system the memory systems main function is to manage wavelet coefficient data, interim code - block attribute data, and temporary work space for creating, parsing, and storing the jpeg2000 code stream. the memory sy stem can also be used for program and data memory for the embedded processor. internal dma engine the internal dma engine provides high bandwidth memory - to - memory transfers, as well as high performance transfers between memory and functional blocks. this f unction is critical for high speed generation and parsing the code stream. data sheet adv202 rev. d | page 27 of 40 adv202 interface there are several possible modes to interface to the adv202 using the vdata bus and the hdata bus or the hdata bus alone. video interface (vda ta bus) the video interface can be used in applications in which uncompressed pixel data is on a separate bus from compressed data. for example, it is possible to use the vdata bus to input uncompressed vide o while using the hdata bus to output the compressed data. this in terface is ideal for applications requiring very high throughput such as live video capture. optionally, the adv202 can compress itu.r - bt656 resolution video on a field - by - field basis or on a two - fields - combined basis , which yields significantly more effic ient compression performance . additionally, high definition digital video such as smpte274m (1080i) is supported using two or more adv202 devices. the video interface can support video data or still image data input/output, 8 - , 10 - , and 12 - bit single or m ultiplexed components. the vdata interface supports digital video in ycbcr format or single component format. ycbcr data must be in 4:2:2 format. video data can be input/output in several different modes on the vdata bus, as described in table 18 . in all these modes, the pixel clock must be input on the vclk pin. table 18 . video input/output modes mode description eav/sav accepts video with embedded eav/sav codes, where the ycbcr data is interleaved onto a single bus. hvf accepts video data accompanied with separate h, v, and f signals where ycbcr data is interleaved onto a single bus. raw v ideo used for still picture data and nonstandard video. vfrm, vstrb, and vrdy are used to program the dimensions of the image. host interface (hdat a bus) the adv202 can connect directly to a wide variety of host processors and asics using an asynchronous sram - style interface, dma accesses, or streaming mode (jdata) interface. the adv202 supports 16 - and 32 - bit buse s for control and 8 - , 16 - , and 32 - bit buses for data transfer. the control and data channel bus widths can be specified independently, which allows the adv202 to support applica - tions that require control and data buses of different widths. the host in terface is used for configuration, control, and status functions, as well as for transferring compressed data streams. it can be used for uncompressed data transfers in certain modes. the host interface can be shared by as many as four concurrent data stre ams in addition to control and status communications. the data streams are ? uncompressed tile data (for example, still image data) ? fully encoded jpeg2000 code stream (or unpackaged code blocks) ? code - block attributes the adv202 uses big endian byte alignment for 16 - and 32 - bit transfers. all data is left - justified (msb). pixel input on the host interface pixel input on the host interface supports 8 - , 10 - , 12 - , 14 - , and 16- bit raw pixel data formats. it can be used for pixel (still image) input/output or compr essed video output. because there are no timing codes or sync signals associated with the input data on the host interface, dimension registers and internal counters are used and must be programmed to indicate the start and end of the frame. see the technical note on using hipi mode f or details on how to use the adv202 in this mode. host bus configuration for maximum flexibility, the host interface provides several configurations to meet particular system r equirements. the default bus mode uses the same pins to transfer control, status, and data to and from the adv202. in this mode, the adv202 can support 16 - and 32 - bit control transfers and 8 - , 16 - , and 32- bit data transfers. the size of these buses can be selected independently, allowing, for example, a 16 - bit microcontroller to configure and control the adv202 while still providing 32- bit data transfers to an asic or external memory system. direct and indirect registers to minimize pin count and cost, t he number of address pins has been limited to four, which yields a total direct address space of 16 locations. these locations are most commonly used by the external controller and are, therefore, accessible directly. all other registers in the adv202 can be accessed indirectly through the iaddr and idata registers. control access regis ters with the exception of the indirect address and data registers (iaddr and idata), all control/status registers in the adv202 are 16 bits wide and are half - word (16 - bit) a ddressable only. when 32 - bit host mode is enabled, the upper 16 bits of the hdata bus are ignored on writes and return all 0s on reads of 16- bit registers. adv202 data sheet rev. d | page 28 of 40 pin configuration an d bus sizes/modes the adv202 provides a wide variety of control and data config urations, which allows it to be used in many applications with little or no glue logic. the following modes are configured using the busmode register. in the following descriptions, host refers to normal addressed accesses ( cs / rd /wr/addr) and data refers to external dma accesses ( dreq / dack ). 32- bit host/32 - bit data in this mode, the hdata[31:0] pins provide full 32 - bit wide data accesses to pixel, code, and attr fifo s. the expanded video interface (vdata) is not available in this mode. 16- bit host/32 - bit data this mode allows a 16 - bit host to configure and communicate with the adv202 while still allowing 32 - bit accesses to the pixel, code, and attr fifos using the ex ternal dma capability. all addressed host accesses are 16 bits and, therefore, use only the hdata[15:0] pins. the hdata[31:16] pins provide the additional 16 bits necessary to support the 32 - bit external dma transfers to and from the fifos only. the expan ded video interface (vdata) is not available in this mode. 16- bit host/16 - bit data this mode uses 16 - bit transfers, if used for host or external dma data transfers. this mode allows for the use of the extended pixel interface modes. 16- bit host/8 - bit data (jdata bus mode) this mode provides separate data input/output and host control interface pins. host control accesses are 16 bits and use hdata[15:0], while the dedicated data bus uses jdata[7:0]. jdata uses a valid/hold synchronous transfer protocol. th e direction of the jdata bus is determined by the mode of the adv202. if the adv202 is encoding (compression), jdata[7:0] is an output. if the adv202 is decoding (decompression), jdata[7:0] is an input. host control accesses remain asynchronous (also refer to the jdata mode section). stage register because the adv202 contains both 16 - bit and 32 - bit registers and its internal memory is mapped as 32 - bit data, a mechanism has been provided to allow 16 - bit hosts to access these regis ters and memory locations using the stage register (stage). stage is accessed as a 16 - bit register using hdata[15:0]. prior to writing to the desired register, the stage register must be written with the upper (most significant) half - word. when the host subsequently writes the lower half - word to the desired control register, hdata is combined with the previously staged value to create the required 32 - bit value that is written. when a register is read, the upper (most significant) half - word is returned imm ediately on hdata and the lower half - word can be retrieved by reading the stage register on a subsequent access. for details on using the stage register, see the adv202 users guide . note that t he stage reg ister does not apply to the three data chan nels (pixel, code, and attr ). these channels are always accessed at the specified data width and do not require the use of the stage register. jdata mode jdata mode is typically used only when the dedicated video interface (vdata) is also enabled. this mode allows code stream data (compressed data compliant with jpeg2000) to be input or output on a single dedicated 8 - bit bus (jdata[7:0]). the bus is always an outpu t during compression operations and is an input du ring decompression. a 2 - pin handshake is used to transfer data over this synchro - nous interface. valid is used to indicate that the adv202 is ready to provide or accept data and is always an output. hold is always an input and is asserted by the host if i t cannot accept/ provide data. for example, jdata mode allows real - time applications, in which pixel data is input over the vdata bus while the compressed data stream is output over the jdata bus. external dma engine the external dma interface is provided to enable high bandwidth data i/o between an external dma controller and the adv202 data fifos. two independent dma channels can each be assigned to any one of the three data stream fifos (pixel, code, or attr). the controller supports asynchronous dma usi ng a data - request/data - acknowledge ( dreq / dack ) protocol in either single or burst access modes. additional functionality is provided for single address compatibility (fly - by) and dedicated chip select (dcs) mod es. adv202 rev. d | page 29 of 40 internal registers this section describes the internal registers of the adv202. direct registers the adv202 has 16 direct registers, as listed in table 19. the direct registers are accessed over the addr [ 3:0], hdata[31:0 ], cs , rd , wr , and ack pins. the host must first initialize the direct registers before any application - specific operation can be implemented. for additional inf ormation on accessing and configuring these registers, see the adv202 users guide . table 19 . direct registers address name description 0x00 pixel pixel fifo access register 0x0 1 code compressed code stream access register 0x02 at tr attribute fifo access register 0x03 reserved reserved 0x04 cmdsta command stack 0x05 eirqie external interrupt enabled 0x06 eirqflg external interrupt flags 0x07 swflag software fla g register 0x08 busmode bus mode configuration register 0x09 mmode miscellaneous mode register 0x0a stage staging register 0x0b iaddr indirect address register 0x0c idata indirect data register 0x0d boot boot mode register 0x0e pll_hi pll control register high byte 0x0f pll_lo pll control register low byte adv202 data sheet rev. d | page 30 of 40 indirect registers in certain modes, such as custom - specific input format or hipi mode, indirect registers must be accessed by the user through the use of the iaddr and idata r egisters. the indirect register address space starts at internal address 0xffff0000. both 32 - bit and 16 - bit hosts can access the indirect registers. 32- bit hosts use the iaddr and idata registers, while the 16- bit hosts use iaddr, idata, and the stage re gister. for additional information on accessing and configuring these registers, see the adv202 users guide . table 20 . indirect registers address name description 0xffff0400 p mode1 pixel/video format 0xffff0404 comp_cnt_status horizontal count 0xffff0408 line_cnt_status vertical count 0xffff040c xtot total samples per line 0xffff0410 ytot total lines per frame 0xffff0414 f0_start start line of field 0 [f0] 0xff ff0418 f1_start start line of field 1 [f1] 0xffff041c v0_start start of active video field 0 [f0] 0xffff0420 v1_start start of active video field 1 [f1] 0xffff0424 v0_end end of active video field 0 [f0] 0xffff0428 v1_end end of active video field 1 [f1] 0xffff042c pixel_start horizontal start of active video 0xffff0430 pixel_end horizontal end of active video 0xffff0440 ms_cnt_del master/slave delay 0xffff0444 reserved reserved 0xffff0448 pmode2 pixel mode 2 0xffff044c vmode video mode 0xffff1408 edmod0 external dma mode register 0 0xffff140c edmod1 external dma mode register 1 0xffff1410 ffthrp fifo threshold for pixel fifo 0xffff1414 reserved reserved 0xffff1418 reserved reserved 0xffff141c ffthrc fifo threshol d for code fifo 0xffff1420 ffthra fifo threshold for attr fifo 0xffff1428 to 0xffff14fc reserved reserved data sheet adv202 rev. d | page 31 of 40 pll the adv202 uses the pll_hi and pll_lo direct registers to configure the pll. any time the pll_lo register is modified, the host must wait at least 20 s before reading or writing to any other register. if this delay is not implemented, erratic behavior could result. the pll can be programmed to have any possible final multiplier value as long as ? jclk > 50 mhz and < 150 mhz (144 - lead versio n). ? jclk > 50 mhz and < 135 mhz (144 - lead version). ? jclk > 50 mhz and < 115 mhz (121 - lead version). ? hclk < 108 mhz (144 - lead , 150 mhz version). ? hclk < 100 mhz (144 - lead , 135 mhz version). ? hclk < 81 mhz (121 - lead version). ? jclk 2 vclk for single - component input. ? jclk 2 vclk for ycrcb [4:2:2] input. ? in jdata mode (jdata), jclk must be 4 mclk or higher. ? for de - interlaced modes, jclk must be 4 mclk. ? the maximum burst freque ncy for external dma modes is 0.36 jclk . ? for mclk frequencies greater than 50 mhz, the input clock divider must be enabled, that is, ipd set to 1. ? ipd cannot be enabled for mclk frequencies below 20 mhz. to achieve the lowest power consumption, an mclk frequency of 27 mhz is recommended for a s tandard definition ccir656 input. the pll circuit is recommended to have a multiplier of 3. this sets jclk and hclk to 81 mhz. 04723-009 lpf phase detect vco jclk hclk ? 2 hclkd ? pllmu l t ? 2 lfb ? 2 ipd by p ass mclk figure 23 . pll architecture and control functions table 21 . recommended pll register settings ipd lfb pllmult hclkd hclk jclk 0 0 n 0 n mclk n mclk 0 0 n 1 n mclk/2 n mclk 0 1 n 0 2 n mclk 2 n mclk 0 1 n 1 n mclk 2 n mclk 1 0 n 0 n mclk/2 n mclk/2 1 0 n 1 n mclk/4 n mclk/2 1 1 n 0 n mclk n mclk 1 1 n 1 n mclk/2 n mclk table 22 . recommended values for pll_hi and pll_lo registers video standard clkin frequency on mclk pll_hi pll_lo smpte125m or itu - r.bt656 (ntsc or pal) 27 mhz 0x0008 0x0004 smpte293m (525p) 27 mhz 0x0008 0x0004 itu - r.bt1358 (625p) 27 mhz 0x0008 0x0004 smpte274m (1080i) 74.25 mhz 0x0008 0x0084 hardware boot the boot mode can be configured via hardware using the cfg pins or via software (see the adv202 users guide ). the first boot mode after power - up is set by the cfg pins. only boot mode 2, boot mode 4, and boot mode 6, described in table 23 , are available via hardware. table 23 . hardware boot modes boot mode settings description hardware boot mode 2 cfg[1] tied high, cfg[2] tied low no - boot host mode. adv202 does not boot, but all internal registers and memory are accessible through normal host i/o operations. for details, see the adv202 users guide and the getting started with the adv202 application note. hardware boot mode 4 cfg[1] tied low, cfg[2] tied high soc boot m ode. hardware boot mode 6 cfg[1] and cfg[2] tied high reserved. adv202 rev. d | page 32 of 40 video input formats the adv202 supports a wide variety of formats for uncompressed video and still image data. the actual interface and bus modes selected for transferring uncompressed data dictates the allowed size of the input data and the number of samples transferred with each access. the host interface can support 8 - , 10 - , 12 - , 14 - , and 16 - bit data formats. the video interface can support video data or still image data input/output. supported forma ts are 8 - , 10 - , 12 - , or 16 - bit single component or ycbcr 4:2:2 formats. see the adv202 users guide f or details. all formats can support less precision than provided by specifying the actual data width/preci sion in the pmode register. the maximum allowable data input rate is limited by using irreversible or reversible compression modes and the data width (or precision) of the input samples. use table 24 and table 25 to determine the maximum data input rate. table 24 . maximum pixel data input rates interface compression mode input format input rate limit active resolution (msps) 1 a pprox min output rate, compressed data 2 (mbps) approx max output rate, compressed data 3 (mbps) 144- lead package hdata irreversible 8 - bit data 45 [40] 130 200 irreversible 10- bit data 45 [40] 130 200 irreversible 12- bit data 45 [40] 130 200 irreversible 16- bit data 45 [40] 130 200 reversible 8 - bit data 40 [36] 130 200 reversible 10- bit data 32 [28] 130 200 reversible 12- bit data 27 [24] 130 200 reversible 14- bit data 23 [20] 130 200 vdata irreversible 8 - bit data 65 [55] 130 200 irreversible 10- bit data 65 [55] 130 200 irreversible 12- bit data 65 [55] 130 200 reversible 8 - bit data 40 [34] 130 200 reversible 10- bit data 32 [28] 130 200 reversible 12- bit data 27 [23] 130 200 121- lead package hdata irreversible 8 - bit data 34 98 150 irreversible 10- bit data 34 98 150 irreversible 12- bit data 34 98 150 irreversible 16- bit data 34 98 150 reversible 8 - bit data 30 98 150 reversible 10- bit data 24 98 150 reversible 12- bit data 20 98 150 rev ersible 14- bit data 17 98 150 vdata irreversible 8 - bit data 48 98 150 irreversible 10- bit data 48 98 150 irreversible 12- bit data 48 98 150 reversible 8 - bit data 30 98 150 reversible 10- bit data 24 98 150 reversible 12- bit data 20 98 150 1 input rate limits for hdata can be less for certain applications depending on input picture size and conte nt, host interface settings, and dma transfer settings. values in brackets refer to the 135 mhz speed grade version of the adv202. 2 minimum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate). 3 m aximum peak output rate, or output rate above this value is not possible . data sheet adv202 rev. d | page 33 of 40 table 25 . maximum supported tile width for data input on hdata and vdata buses compression mode input format tile/precinct maximum width 9/7i single - component 2048 9/7i two - component 1024 each 9/7i three - componen t 1024 (y) 5/3i single - component 4096 5/3i two - component 2048 (each) 5/3i three - component 2048 (y) 5/3r single - component 4096 5/3r two - component 2048 5/3r three - component 1024 adv202 data sheet rev. d | page 34 of 40 applications this section describes typical video applications fo r the adv202 jpeg2000 video processor. encode multichip mode due to the data input rate limitation (see table 24 ), an 1080i application requires at least two adv202s to encode or decode full - resolution 1080i video. in encode mod e, the adv202 accepts y and cbcr data on separate buses. the input data must be in eav/sav format. an encode example is shown in figure 24. in decode mode, a master/slave configuration (as shown in figu re 25 ) or a slave/slave configuration can be used to synchronize the outputs of the two adv202s. see an - 796 adv202 multichip application application note for details on how to configure the adv202s in a m ultichip application. applications that have two separate vdata outputs sent to an fpga or buffer before they are sent to an encoder do not require synchronization at the adv202 outputs 04723-002 dat a[31:0] hd at a[31:0] addr[3:0] addr[3:0] cs cs rd rd wr we ack ack irq cs rd wr ack irq dreq dack irq dreq dreq field vsync hsync dack dack g i/o scomm[5] vclk 1080i video in mclk vdat a[ 1 1:2] 32-bit host cpu 10-bit sd/hd video decoder adv202 _1_sl a ve scomm[5] hd at a[31:0] addr[3:0] cs rd we ack irq field vsync hsync dreq dack vclk mclk vdat a[ 1 1:2] adv202 _2_sl a ve llc y[9:0] c[9:0] cbcr cbcr y figure 24 . encode multichip application data sheet adv202 rev. d | page 35 of 40 decode multichip master/sla ve i n a master/slave configuration, it is expected that the master hvf outputs are connected to the slave hvf inputs and that each scomm[5] pin is connected to the same gpio on the host. in a slave/slave configuration, the c ommon hvf for both adv202s is generated by an external house sync , and each scomm[5] is connected to the same gpio output on the host. swirq1, software interrupt 1 in the eirqie register, must be unmasked on both devices to enable multichip mode. 04723-003 dat a[31:0] hd at a[31:0] addr[3:0] addr[3:0] cs cs rd rd wr we ack ack irq cs rd wr ack irq dreq dack irq dreq dreq field vsync hsync dack dack g i/o scomm[5] vclk 1080i video out mclk vdat a[ 1 1:2] 32-bit host cpu 10-bit sd/hd video encoder adv202 _1_master scomm[5] hd at a[31:0] addr[3:0] cs rd we ack irq field vsync hsync dreq dack vclk mclk vdat a[ 1 1:2] adv202 clkin y[9:0] c[9:0] cbcr cbcr y y 74.25mhz osc figu re 25 . decode multichip master/slave application digital still camera /camcorder figure 26 is a typical configuration for a digital camera or camcorder. 04723-004 d[9:0] 10 da t a inputs[9:0] mclk vclk vfrm vrdy vstrb vda t a[1 5:6] sda t a serial da t a sck serial clk sl serial en ad9843a fpga 16-bit host cpu adv202 da t a[15:0] hda t a[15:0] addr[3:0] addr[3:0] cs cs rd rd we we ack ack irq irq figure 26 . digital sti ll camera/camcorder encode application for 10 - bit pixel data using raw pixel mode adv202 data sheet rev. d | page 36 of 40 encode/decode sdtv v ideo application figure 27 shows two adv202 chips using 10 - bit ccir656 in normal host mode. 04723-005 encode mode 32-bit host cpu adv202 hd at a[31:0] dat a[31:0] 10-bit video decoder irq intr addr[3:0] addr[3:0] p[19:10] vdat a[ 1 1:2] video in llc1 vclk mclk cs cs rd rd we we ack ack 27mhz osc decode mode 32-bit host cpu adv202 hd at a[31:0] dat a[31:0] 10-bit video encoder irq intr addr[3:0] addr[3:0] p[9:0] vdat a[ 1 1:2] video out clkin vclk mclk cs cs rd rd we we ack ack figure 27 . encode/decode sdtv video application data sheet adv202 rev. d | page 37 of 40 asic application (32 - bit host/32 - bit asic) figure 28 shows two adv202 chips using 10 - bit ccir656 in normal host mode. 04723-006 encode mode 32-bit host cpu adv202 dat a[31:0] irq irq addr[3:0] addr[3:0] cs cs rd rd we we ack ack asic 10-bit video decoder p[19:10] llc1 vdat a[ 1 1:2] video in vclk mclk dreq0 dreq0 dack0 dack0 hd at a[31:0] dat a[31:0] 27mhz osc decode mode 31 -bit host cpu adv202 dat a[31:0] irq irq addr[3:0] addr[3:0] cs cs rd rd we we ack ack asic 10-bit video encoder p[9:0] vdat a[ 1 1:2] video out clkin vclk mclk dreq0 dreq0 dack0 dack0 hd at a[31:0] d at a[31:0] figure 28 . encode/decode asic applicatio n adv202 data sheet rev. d | page 38 of 40 hipi (host interface pixel interface) figure 29 is a typical configuration using hipi mode. 04723-007 hd at a<31> y0/g0 data sheet adv202 rev. d | page 39 of 40 outline dimensions *compliant with jedec s t andards mo-192-abd-1 with exception to package height and thickness. detail a 0.70 0.60 0.50 ball diameter 0.20 coplanarity 1.00 bsc 10.00 bsc sq a b c d e f g h j k l 10 8 7 6 3 2 1 9 5 4 11 * 1.31 1.21 1.11 a1 corner index area top view ball a1 corner detail a bottom view 0.50 nom 0.30 min * 1.85 1.71 1.40 12.20 12.00 sq 11.80 082406-a seating plane figure 31 . 121 - lead chip scale package ball grid arr ay [csp _ bga] (bc - 121 - 1) dimensions shown in millimeters seating plane detail a 0.70 0.60 0.50 ball diameter coplanarity 0.20 max 1.00 bsc 11.00 bcs sq a b c d e f g j h k l m 12 11 10 8 7 6 3 2 1 9 5 4 0.53 0.43 a1 corner index area top view 13 .00 bsc sq ball a1 indicator detail a bottom view * 1.85 max * 1.32 1.21 1.11 * compliant with jedec standards mo-192-aad-1 with exception to package height and thickness. 021506- a figure 32 . 144 - lead chip scale package ball grid array [csp _ bga] (bc - 144 - 3) dimensions shown in millimeters adv202 data sheet rev. d | page 40 of 40 ordering guide model 1 temperature range speed grade operati ng voltage package description package option adv202bbcz - 115 ?40c to +85c 115 mhz 1.5 v internal, 2.5 v or 3.3 v i/o 121- lead csp _ bga bc -121-1 adv202bbczrl - 115 ?40c to +85c 115 mhz 1.5 v internal, 2.5 v or 3.3 v i/o 121- lead csp _ bga bc -121-1 adv202b bcz - 135 ?40c to +85c 135 mhz 1.5 v internal, 2.5 v or 3.3 v i/o 144- lead csp _ bga bc -144-3 adv202bbcz - 150 ?40c to +85c 150 mhz 1.5 v internal, 2.5 v or 3.3 v i/o 144- lead csp _ bga bc -144-3 adv202bbczrl - 150 ?40c to +85c 150 mhz 1.5 v internal, 2.5 v o r 3.3 v i/o 144- lead csp _ bga bc -144-3 1 z = rohs compliant part. ? 2006 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04723 - 0 - 1/12(d) |
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